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Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Three 3.3V LVPECL outputs on two banks, A Bank with one LVPECL pair and B Bank with 2 LVPECL output pairs * Using a 31.25MHz or 26.041666 crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * VCO range: 560MHz to 700MHz * RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.51ps (typical) * RMS phase noise at 156.25MHz Phase noise: Offset Noise Power 100Hz ............... -96.8 dBc/Hz 1KHz .............. -119.1 dBc/Hz 10KHz .............. -126.4 dBc/Hz 100KHz .............. -127.0 dBc/Hz * Full 3.3V supply mode * 0C to 70C ambient operating temperature * Industrial temperature available upon request
GENERAL DESCRIPTION
The ICS843003 is a 3 differential output LVPECL Synthesizer designed to generate Ethernet referHiPerClockSTM ence clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 843003 has 2 output banks, Bank A with 1 differential LVPECL output pair and Bank B with 2 differential LVPECL output pairs.
ICS
The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS843003 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843003 is packaged in a small 24-pin TSSOP package.
PIN ASSIGNMENT
DIV_SELB0 VCO_SEL MR VCCO_A QA0 nQA0 OEB OEA FB_DIV VCCA VCC DIV_SELA0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DIV_SELB1 VCCO_B QB0 nQB0 QB1 nQB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT VEE DIV_SELA1
BLOCK DIAGRAM
OEA Pullup DIV_SELA[1:0] VCO_SEL
Pullup
ICS843003
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package QA0 Top View
nQA0
TEST_CLK Pulldown
0
00 01 0 10 11
/1 /2 (default) /4 /5
XTAL_IN
OSC
XTAL_OUT XTAL_SEL Pullup
1
Phase Detector
VCO 625MHz
1
QB0
FB_DIV 0 = /20 (default) 1 = /24
00 01 10 11
/1 /2 /4 (default) /5
nQB0 QB1 nQB1
FB_DIV Pulldown DIV_SELB[1:0] MR Pulldown OEB Pullup
843003AG
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REV. A JULY 27, 2004
Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Description Division select pin for Bank B. Default = Low. Pulldown LVCMOS/LVTTL interface levels. VCO select pin. When Low, the PLL is bypassed and the cr ystal reference or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the Pullup output dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. Output supply pin for Bank A outputs. Differential output pair. LVPECL interface levels. Output enable Bank B. Active High output enable. When logic HIGH, the output pair on Bank B is enabled. When logic LOW, the output pair drives differential Low (QB0=Low, nQB0=High). Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. Output enable Bank A. Active High output enable. When logic HIGH, the 2 output pairs on Bank A are enabled. When logic LOW, the output pair drives differential Low (QA0=Low, nQA0=High). Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. Feedback divide select. When Low (default), the feedback divider is set for /20. When HIGH, the feedback divider is set for /24. LVCMOS/LVTTL interface levels. Analog supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 Name DIV_SELB0 Input
2
VCO_SEL
Input
3
MR
Input
4 5, 6
VCCO_A QA0, nQA0
Power Ouput
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9 10 11 12 13 14 15, 16
FB_DIV VCCA VCC DIV_SELA0 DIV_SELA1 VEE XTAL_OUT, XTAL_IN TEST_CLK
Input Power Power Input Input Power Input
Pulldown
17
Input
18 19, 20 21, 22 23
XTAL_SEL nQB1, QB1 nQB0, QB0 VCCO_B
Input Output Output Power
Core supply pin. Division select pin for Bank A. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. Division select pin for Bank A. Default = Low. Pulldown LVCMOS/LVTTL interface levels. Negative supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. XTAL_IN is also the overdrive pin if you want to overdrive the cr ystal circuit with a single-ended reference clock. Single-ended reference clock input. Has an internal pulldown resistor to Pulldown pull to low state by default. Can leave floating if using the cr ystal interface. LVCMOS/LVTTL interface levels. Cr ystal select pin. Selects between the single-ended TEST_CLK or cr ystal Pullup interface. Has an internal pullup resistor so the cr ystal interface is selected by default. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
Output supply pin for Bank B outputs. Division select pin for Bank B. Default = High. 24 DIV_SELB1 Input Pullup LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
843003AG
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REV. A JULY 27, 2004
Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor
TABLE 3A. BANK A FREQUENCY TABLE
Inputs Crystal Frequency 31.25 31.25 31.25 31.25 26.041666 26.041666 26.041666 26.041666 DIV_SELA1 0 0 1 1 0 0 1 1 DIV_SELA0 0 1 0 1 0 1 0 1 FB_DIV 0 0 0 0 1 1 1 1 Feedback Divider 20 20 20 20 24 24 24 24 Bank A Output Divider 1 2 4 5 1 2 4 5 M/N Multiplication Factor 20 10 5 4 24 12 6 4.8 QA0/nQA0 Output Frequency 625 312.5 156.25 125 625 312.5 156.25 125
TABLE 3B. BANK B FREQUENCY TABLE
Inputs Crystal Frequency 31.25 31.25 31.25 31.25 26.041666 26.041666 26.041666 26.041666 DIV_SELA1 0 0 1 1 0 0 1 1 DIV_SELA0 0 1 0 1 0 1 0 1 FB_DIV 0 0 0 0 1 1 1 1 Feedback Divider 20 20 20 20 24 24 24 24 Bank B Output Divider 1 2 4 5 1 2 4 5 M/N Multiplication Factor 20 10 5 4 24 12 6 4.8 QBx/nQBx Output Frequency 625 312.5 156.25 125 625 312.5 156.25 125
843003AG
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REV. A JULY 27, 2004
Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Outputs QA /1 /2 /4 /5 Inputs DIV_SELB1 0 0 1 1 DIV_SELB0 0 1 0 1 Outputs QB /1 /2 /4 /5
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs DIV_SELA1 0 0 1 1 DIV_SELA0 0 1 0 1
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs FB_DIV 0 1 Feedback Divide /20 /24
Disabled
Enabled
TEST_CLK
OEA, OEB
nQA0, nQBx QA0, QBx
FIGURE 1. OE TIMING DIAGRAM
843003AG
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REV. A JULY 27, 2004
Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO_A, B I EE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Included in IEE Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 158 15 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage DIV_SELA0:A1, FB_DIV DIV_SELB0:B1, VCO_SEL, Input Low Voltage MR, OEA, OEB, XTAL_SEL TEST_CLK TEST_CLK, MR, FB_DIV DIV_SELA1, DIV_SELB0 Input High Current DIV_SELB1, DIV_SELA0, VCO_SEL, XTAL_SEL, OEA, OEB TEST_CLK, MR, FB_DIV DIV_SELA1, DIV_SELB0 Input Low Current DIV_SELB1, DIV_SELA0, VCO_SEL, XTAL_SEL, OEA, OEB Test Conditions Minimum 2 -0.3 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Typical Maximum VCC + 0.3 0.8 1.3 150 5 Units V V V A A A A
IIH
IIL
843003AG
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REV. A JULY 27, 2004
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ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency FB_DIV = /20 FB_DIV = /24 28 23.33 Test Conditions Minimum Typical Fundamental 31.25 26.04166 35 29.167 50 7 MHz MHz pF Maximum Units
Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions DIV_SELx[1:0] = 00 fOUT Output Frequency Range DIV_SELx[1:0] = 01 DIV_SELx[1:0] = 10 DIV_SELx[1:0] = 11 Minimum 560 280 140 112 Typical Maximum 700 350 175 140 20 Outputs @ Same Frequency Outputs @ Different Frequencies 625MHz (1.875MHz - 20MHz) 0.42 0.50 0.51 0.52 250 600 60 53 312.5MHz (1.875MHz - 20MHz) 156.25MHz (1.875MHz - 20MHz) 125MHz (1.875MHz - 20MHz) tR / tF Output Rise/Fall Time 20% to 80% 35 100 Units MHz MHz MHz MHz ps ps ps ps ps ps ps ps % %
tsk(b) tsk(o)
Bank Skew, NOTE 1 Output Skew; NOTE 2, 4
tjit(O)
RMS Phase Jitter (Random); NOTE 3
DIV_SELx[1:0] = 00 40 odc Output Duty Cycle DIV_SELx[1:0] 00 47 NOTE 1: Defined as skew winthin a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
843003AG
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REV. A JULY 27, 2004
Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 125MHZ
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
10Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.52ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
TYPICAL PHASE NOISE AT 156.25MHZ
0 -10 -20 -30 -40 -50 -60
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.51ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
-160
OFFSET FREQUENCY (HZ)
843003AG
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REV. A JULY 27, 2004
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ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 312.5MHZ
0 -10 -20 -30 -40 -50 -60
10Gb Ethernet Filter 312.5MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.50ps (typical)
NOISE POWER dBc Hz
-70 -80 -90 -100
Raw Phase Noise Data
-110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k
10k
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 625MHZ
0 -10 -20 -30 -40 -50 -60
10Gb Ethernet Filter 625MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.42ps (typical)
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
Raw Phase Noise Data
843003AG
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Phase Noise Result by adding 10Gb Ethernet Filterto raw data OFFSET FREQUENCY (HZ)
REV. A JULY 27, 2004
Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
V CC, VCCA, VCCO_A. _B
Qx
SCOPE
nQx Qx nQy
LVPECL
nQx
Qy
tsk(o)
VEE
-1.3V0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
nQB0
Noise Power
QB0 nQB1 QB1
Phase Noise Mask
tsk(b)
f1 Offset Frequency f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
BANK SKEW
nQA0, nQB0, nQB1 QA0, QB0, QB1 80%
Pulse Width t
PERIOD
80% VSW I N G
Clock Outputs
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843003AG
OUTPUT RISE/FALL TIME
REV. A JULY 27, 2004
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Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843003 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843003 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 31.25MHz or 26.041666MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
ICS843003
Figure 3. CRYSTAL INPUt INTERFACE
843003AG
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REV. A JULY 27, 2004
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ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
Zo = 50 84 84
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
843003AG
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REV. A JULY 27, 2004
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ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
pF parallel resonant 31.25MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. The C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
LAYOUT GUIDELINE
Figure 5A shows a schematic example of the ICS843003. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18
3.3V
VCC
VCCA
R2 10
Zo = 50 Ohm
R3 133
R5 133
C3 10uF
C4 0.01u
VCC
VCCO
C6 0.1u
+
Zo = 50 Ohm
12 11 10 9 8 7 6 5 4 3 2 1
Logic Control Input Examples
VDD
C7 0.1u
-
VDD
To Logic Input pins
RD1 Not Install
DIV_SELA1 VEE XTAL_OUT XTAL_IN TEST_CLK XTAL_SEL nQB1 QB1 nQB0 QB0 VCCO_B DIV_SELB1
RU1 1K
RU2 Not Install
DIV_SELA0 VCC VCCA FB_DIV OEA OEB nQA0 QA0 VCCO_A MR VCO_SEL DIV_SELB0
Set Logic Input to '1'
Set Logic Input to '0'
R4 82.5
R6 82.5
To Logic Input pins
RD2 1K
VCC=3.3V
3.3V
U1 ICS843003
VCCO=3.3V
R7 133
Zo = 50 Ohm
R9 133
VCCO
13 14 15 16 17 18 19 20 21 22 23 24
+
Zo = 50 Ohm
-
C2 33pF
X1 31.25MHz 18pF
C1 27pF
C8 0.1u
R8 82.5
R10 82.5
FIGURE 5A. ICS843003 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 5B shows an example of ICS843003 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed
in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane.
TABLE 7. FOOTPRINT TABLE
Reference C1, C2 C3 C4, C5, C6, C7, C8 Size 0402 0805 0603
R2 0603 NOTE: Table 7, lists component sizes shown in this layout example.
FIGURE 5B. ICS843003 PC BOARD LAYOUT EXAMPLE
843003AG
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REV. A JULY 27, 2004
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ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843003. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843003 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 158mA = 547.5mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 30mW = 90mW
Total Power_MAX (3.465V, with all outputs switching) = 547.5mW + 90mW = 637.5mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.638W * 65C/W = 111.5C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE JA
FOR
24-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
843003AG
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ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (V
CCO_MAX
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843003AG
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ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 9. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS843003 is: 3767
843003AG
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REV. A JULY 27, 2004
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ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 10. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
843003AG
www.icst.com/products/hiperclocks.html
16
REV. A JULY 27, 2004
Integrated Circuit Systems, Inc.
ICS843003
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS843003AG ICS843003AG Package 24 Lead TSSOP 24 Lead TSSOP on Tape and Reel Count 60 per tube 2500 Temperature 0C to 70C 0C to 70C
TABLE 11. ORDERING INFORMATION
Part/Order Number ICS843003AG ICS843003AGT
The aforementioned trademarks, HiPerClockSTM
and FemtoClocksTM
are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843003AG
www.icst.com/products/hiperclocks.html
17
REV. A JULY 27, 2004

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